Update README.md

README.md

@@ -42,13 +42,6 @@ The dataset is created for research purposes and consists of source code from a
   "size": "217",
   "content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t     b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
   "license": "mit"
-}, {
-  "repo_name": "cybernet14/linguist",
-  "path": "samples/VHDL/foo.vhd",
-  "copies": "91",
-  "size": "217",
-  "content": "-- VHDL example file\n\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n\nentity inverter is\n\tport(a : in std_logic;\n\t     b : out std_logic);\nend entity;\n\narchitecture rtl of inverter is\nbegin\n\tb \u003c\u003d not a;\nend architecture;\n",
-  "license": "mit"
 }
 ```